CPU & Processor Reference
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CPU & Processor Reference · 2026
01 Instruction Set Architectures the ISA decides what software runs · not the brand or socket
| ISA | First spec | Where in 2026 | SIMD ceiling | Status |
|---|---|---|---|---|
| x86-64 aka AMD64, Intel 64 | 2000 | Intel Core / Xeon, AMD Ryzen / EPYC / Threadripper, standard Windows / Linux desktops + most servers | AVX-512 / AVX10 / AMX | Current dominant on desktop & server |
| ARM64 aka AArch64, ARMv8/v9 | 2011 | Apple M-series, Qualcomm Snapdragon X, Ampere, AWS Graviton, NVIDIA Grace, all phones, Raspberry Pi 5 | NEON / SVE2 / SME | Current rising on laptop & cloud |
| RISC-V RV64GC + ext. | 2010 | SiFive, Tenstorrent, Alibaba T-Head, embedded MCUs, accelerator control planes, Linux SBCs | V (vector) ext. | Current embedded · niche on desktop |
| POWER / PowerPC | 1991 | IBM Power10/11 mainframes & HPC, OpenPOWER ecosystem | VSX, MMA | Legacy enterprise niche |
| x86 (32-bit) IA-32 | 1985 | Legacy Windows apps in compat mode, retro / embedded systems | SSE2 | Obsolete Intel dropping in 2027+ |
02 Desktop CPU Lineups · 2026 x3d = stacked L3 · refresh = same socket, tweaked silicon
| Family | Socket | Node | Cores (P+E) | Memory | Notes |
|---|---|---|---|---|---|
| Intel Core Ultra 200S Arrow Lake | LGA 1851 | TSMC N3B | up to 8P + 16E | DDR5-6400 | NPU on-die, big efficiency gain over 14th gen, weaker gaming than X3D |
| Intel Core Ultra 200S Plus Arrow Lake Refresh | LGA 1851 | TSMC N3B | up to 8P + 16E | DDR5-6800 | Spring 2026 refresh · stronger single-thread · same socket |
| AMD Ryzen 9000 Zen 5 | AM5 | TSMC N4P | 6 to 16 (no E) | DDR5-6000 | Best productivity per dollar · AVX-512 native · AM5 socket roadmap through 2027+ |
| AMD Ryzen 9000X3D 9800X3D / 9950X3D / 9850X3D refresh | AM5 | TSMC N4P | 8 / 12 / 16 | DDR5-6000 | 3D V-Cache stacked L3 · fastest gaming CPU class · 20–35% over Intel in CPU-bound titles |
| AMD Threadripper 9000 Zen 5 | sTR5 | TSMC N4P | 24 to 96 | 8-ch DDR5 ECC | HEDT / workstation · PCIe 5.0 ×128 · rendering, simulation, large-model fine-tunes |
| Intel Bartlett Lake-S gaming-focused | LGA 1700 | Intel 7 | up to 12P | DDR5 / DDR4 | P-cores only revival · drop-in for 12/13/14-gen boards · niche |
03 Laptop & Mobile CPU Lineups · 2026 soldered BGA · TOPS = NPU throughput · Copilot+ baseline 40 TOPS
| Family | ISA | Node | Cores | NPU | Notes |
|---|---|---|---|---|---|
| Intel Core Ultra 300 Panther Lake · Jan 2026 | x86-64 | Intel 18A | up to 16 (P+E+LP-E) | ~50 TOPS | First consumer 18A part · Xe3 Arc iGPU · efficient AI PCs · Copilot+ certified |
| Intel Core Ultra 200V Lunar Lake | x86-64 | TSMC N3B | 4P + 4E | 48 TOPS | Thin-and-light · on-package LPDDR5X · long battery, no Hyper-Threading |
| AMD Ryzen AI 400 Gorgon Point · 2026 | x86-64 | TSMC N4P | up to 12 Zen 5+5c | 50+ TOPS | Radeon 890M iGPU · 15–20% over Ryzen AI 300 · Copilot+ certified |
| AMD Ryzen AI Max+ Strix Halo | x86-64 | TSMC N4P | 16 Zen 5 | 50 TOPS | Workstation-class APU · 40 RDNA 3.5 CUs · 128 GB unified · rivals dGPU laptops |
| Apple M5 / M5 Pro / M5 Max 2025–2026 | ARM64 | TSMC N3P | 10 / 14 / 16 | ~38 TOPS | Best perf-per-watt class · unified memory up to 128 GB on Max · Neural Engine in every GPU core |
| Qualcomm Snapdragon X2 Elite / Extreme Oryon Gen 3 · H1 2026 | ARM64 | TSMC N3 | 12 to 18 (no E) | 80 TOPS | Highest NPU on market · up to 128 GB LPDDR5X · Windows-on-ARM Copilot+ flagship |
| NVIDIA N1 / N1X Windows-on-ARM · 2026 | ARM64 | TSMC N3 | TBD | TBD | NVIDIA’s first ARM desktop/laptop SoC · paired with Blackwell-class GPU · CES/Computex 2026 debut |
04 Server CPUs · 2026 P vs E vs ARM · TCO is cores × power × license
| Family | Cores | Memory |
|---|---|---|
| Intel Xeon 6 P Granite Rapids | up to 128 P | 12-ch DDR5 / MRDIMM |
| Intel Xeon 6 E Sierra Forest | up to 288 E | 12-ch DDR5 |
| Intel Clearwater Forest H2 2026 · 18A | 288 E refresh | 12-ch DDR5 |
| AMD EPYC 9005 Turin · Zen 5 / 5c | up to 192 Zen 5c | 12-ch DDR5-6400 |
| Ampere AmpereOne | up to 192 | 8-ch DDR5 |
| AWS Graviton 4 Neoverse V2 | 96 | 12-ch DDR5 |
| NVIDIA Grace Neoverse V2 | 72 | LPDDR5X 480 GB |
Rule of thumb: P-cores for low-latency & per-core licensing (Oracle, SQL Server) · E-core / ARM for max cores per rack & per-watt. Grace pairs with Hopper/Blackwell over NVLink-C2C.
05 Process Nodes & Sockets “nm” is marketing · density & SRAM scaling matter
| Node | Used by | Status |
|---|---|---|
| TSMC N3 / N3E / N3P | Apple M3–M5, Snapdragon X / X2, Intel Arrow Lake | Current |
| TSMC N4 / N4P | Ryzen 9000, Ryzen AI 300/400, EPYC Turin | Current |
| Intel 18A RibbonFET + PowerVia | Panther Lake (Core Ultra 300), Clearwater Forest, Nova Lake | New Jan 2026 ramp |
| TSMC N2 gate-all-around | Late 2026 / 2027 silicon · Apple M6, Zen 6 server | Sampling |
| Intel 7 | 12/13/14-gen Core, Bartlett Lake-S | Legacy |
Sockets: LGA 1851 (Intel desktop) · AM5 (AMD desktop, 2022–2027+) · sTR5 (Threadripper) · SP5 / LGA 4677 (EPYC / Xeon 6) · BGA soldered (Apple, most Snapdragon X). AM6 expected with Zen 6.
06 Workload × CPU Family · Where Each Shines approximate · 2026 retail · GPU not factored
| Workload | Ryzen X3D | Ryzen 9000 | Threadripper | Core Ultra 200S Plus | Panther Lake | Apple M5 | Snapdragon X2 |
|---|---|---|---|---|---|---|---|
| AAA gaming · 1080p/1440p | |||||||
| Productivity multi-thread | |||||||
| Single-thread / latency | |||||||
| Content creation · CPU encode | |||||||
| Compiles · large codebase | |||||||
| Local LLM inference (NPU) | |||||||
| Battery life · mobile | |||||||
| Windows app compatibility | |||||||
| macOS-only software | |||||||
| Virtualisation · many VMs |
07 Key Architectural Features what changes between generations under the marketing
| Feature | What it is · why it matters |
|---|---|
| Hybrid cores (P + E) | Intel since 12th gen, ARM forever, Apple since M1. Big cores for latency, small cores for parallel work + power. Scheduler (Thread Director on Intel) decides. AMD desktop is still all-P; Ryzen 9000 has no E-cores, EPYC uses Zen 5c (dense, lower clock). |
| 3D V-Cache (X3D) | AMD stacks a second L3 die on top of the CCD. 96–192 MB total L3. Game engines + simulators with hot working sets see 20–35% uplift; cold-cache productivity sees little. |
| AVX-512 / AVX10 / AMX | 512-bit SIMD. AMD has it on Zen 4/5 (full-width on 5). Intel removed it from consumer Alder/Raptor Lake, added back via AVX10 (variable width). AMX = matrix multiply, Intel Xeon only. Matters for AI/HPC code. |
| SVE2 / SME | ARM’s variable-length SIMD + Scalable Matrix Extension. Apple M4+ and Neoverse V2/V3 have it. The future of ARM HPC and on-device inference. |
| NPU · TOPS | Dedicated low-power matrix engine. Copilot+ baseline 40 TOPS · Snapdragon X2 Extreme 80 · Apple M5 ~38 · Ryzen AI 50+ · Panther Lake 50. Used for Recall, Studio Effects, on-device Whisper/Phi/Llama. |
| Chiplets · advanced packaging | AMD (CCD + IOD), Intel Foveros (tiles), Apple UltraFusion. Decouples logic from I/O, allows mixing nodes. Power and latency cost crossing dies; mature on AMD, improving on Intel. |
| PCIe & DDR generations | 2026 mainstream: PCIe 5.0 ×16 + DDR5-6000/6400. Server PCIe 6.0 shipping (EPYC Turin, Xeon 6). PCIe 7.0 ratified, silicon expected late 2026+. DDR6 spec finalised, products 2027+. |
| TDP · PL1 / PL2 / PBP / MTP | Marketing TDP ≠ actual power. Intel: PBP (base) and MTP (max turbo). AMD: TDP and PPT. A “65 W” CPU often pulls 120 W+ in turbo. Cooler sizing must target MTP/PPT, not the box number. |
08 Quick Picks match task → CPU · pricing mid-2026 · USD MSRP
Pure gaming desktop
Ryzen 7 9800X3D
~$440 · class-leading FPS · 8 cores enough for any game today.
Gaming + content creation
Ryzen 9 9950X3D
~$640 · 16 cores + V-Cache · the do-everything desktop.
Productivity / dev workstation
Ryzen 9 9950X or Core Ultra 9 285K
Max multi-thread without HEDT pricing.
Rendering / simulation
Threadripper 9970X / 9980X
32–64 cores, 8-channel ECC, PCIe 5.0 ×128.
Thin-and-light Win laptop
Core Ultra 300 (Panther Lake)
Best x86 efficiency + Xe3 iGPU + 50 TOPS NPU.
ARM Windows · max battery
Snapdragon X2 Elite Extreme
Highest NPU on market · 14–16 h real use.
Mac · pro creative
MacBook Pro M5 Max
Up to 128 GB unified · class-leading GPU/render.
Homelab · power-efficient
Ryzen 9700 / Core Ultra 5 245
65 W tier · ECC on AM5 with Pro / Server boards.
Cloud · per-vCPU cost
Graviton 4 / AmpereOne
~20–40% cheaper than x86 for stateless web/microservices.
09 Critical Gotchas the small print that wastes money or breaks builds
“TDP” lies — cooler for MTP / PPTA “65 W” Ryzen 9700X pulls ~88 W (PPT). A “125 W” Core Ultra 9 285K can hit 250 W+ MTP. Always cool for the turbo envelope, not the base. Marketing TDP is now closer to a category label than a power figure.
X3D is not a free upgrade for everyoneThe 3D V-Cache only helps cache-sensitive workloads (games, sims, databases). Cold-cache video encode, compiles, and rendering see no benefit — sometimes a slight regression from the lower boost clock. Buy non-X3D for productivity.
13th / 14th gen Intel instabilityA microcode bug caused permanent voltage degradation on many 13900K / 14900K CPUs. Intel issued microcode 0x12B and extended warranty to 5 years. Update BIOS to a 0x12B-or-later microcode before heavy use; check serial against the affected range.
Hybrid scheduler still hates Linux nichesWindows 11 schedules P/E cores well. Linux improved in 6.x but some workloads (game emulators, real-time audio, older VMs) still pin to E-cores wrongly. Set
cpuset or pin manually; check htop shows the right cluster.Apple Silicon is not upgradableRAM, SSD, GPU — all soldered or on-package. Order the max you’ll need at purchase. 8 GB is genuinely too little in 2026; 24/32 GB is the new floor for any work beyond browsing.
Windows-on-ARM still has app gapsNative ARM coverage is ~90% of common apps. Anti-cheat (Vanguard, EAC, BattlEye) is partial. Some pro tools (older Adobe plug-ins, specific CAD, VPN clients, drivers) still x64-only and run via Prism translation — slower & sometimes broken. Test your stack before committing.
DDR5 timings matter more than tierOn AM5, DDR5-6000 CL30 beats DDR5-7200 CL36 in most workloads because of the 2:1 memory-controller ratio fallback above 6400. Don’t chase headline MT/s — buy the kit on the motherboard QVL.
ECC support is fragmentedECC works on AM5 with most chipsets + AGESA, but only validated on AMD Pro / server boards. Intel locks ECC to Xeon + W-series chipsets. EPYC and Xeon always. If uptime matters, don’t assume — check the board manual.
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